module uart_loop (
    input              clk,
    input              rst_n,
    input              rx,
    input    [1:0]     sw,
    output   [7:0]     data,
    output             tx
);
//wire      [7:0]          data;
wire                     tx_done;

uart_rx inst_uart_rx (
    .clk(clk),
    .rst_n(rst_n),
    .rx(rx),
    .sw(sw),
    .rx_data(data),
    .rx_done(rx_done)
);

uart_tx inst_uart_tx (
    .clk(clk),
    .rst_n(rst_n),
    .tx_data(data),
    .tx_start(rx_done),
    .sw(sw),
    .tx(tx),
    .tx_done(tx_done)
);

endmodule